1. Field of the Invention
The embodiments of the invention generally relate to planar field effect transistors (FETs) and, more particularly, to a method of forming a planar FET with embedded and faceted source/drain stressors on a silicon-on-insulator (SOI) wafer, a planar FET structure and a design structure for the planar FET.
2. Description of the Related Art
Charge carrier mobility impacts current flowing through the channel region of field effect transistors (FETs). That is, in n-type field effect transistors (NFETS) current flow is proportional to the mobility of electrons in the channel region, whereas in p-type field effect transistors (PFETs) current flow is proportional to the mobility of holes in that channel region. Stress can be imposed upon on the channel region in order to adjust carrier mobility and, thereby, adjust current flow. Specifically, compressive stress on the channel region of a PFET can enhance hole mobility and, thereby increase drive current. Contrarily, tensile stress on the channel region of an NFET can enhance electron mobility and, thereby increase drive current.
Various stress engineering techniques are known for imparting the desired stress on PFET and NFET channel regions including, but not limited to, the use of source/drain stressors. For example, as discussed in U.S. Pat. No. 6,885,084 of Murthy et al. issued on Apr. 26, 2005 and incorporated herein by reference, a compressive stress (i.e., a uni-axial compressive strain parallel to the direction of the current) can be created in the channel region of a planar PFET by forming the source/drain regions with an epitaxially grown alloy of, for example, Silicon and Germanium. Similarly, a tensile stress (i.e., a uni-axial tensile strain parallel to the direction of the current) can be created in the channel region of a planar NFET by forming the source/drain regions with an epitaxially grown alloy of, for example, Silicon and Carbon. Additionally, in both PFETs and NFETs the shape (i.e., the profile) of the interface between the source/drain stressors and the channel region can have an impact on the stress imparted on the channel region. For example, on bulk wafers, increased stress can be imparted on the channel region of a FET, if the source/drain stressor material is epitaxially grown in recesses having faceted sidewalls adjacent to the channel region. Unfortunately, this technique is incompatible with silicon-on-insulator (SOI) wafers and, more particularly, incompatible with current state of the art thin SOI (e.g., 45-110 nm SOI) wafers and ultra-thin SOI (e.g., sub-45 nm SOI) wafers.